DESIGN LINKED INCENTIVE SCHEME

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The Government of India highlighted the progress of the Design Linked Incentive (DLI) Scheme under the Semicon India Programme in January 2026.
DLI-supported chip design projects have shown strong outcomes, including tape-outs, patents, and growing private investment.
The scheme is emerging as a key pillar of India’s self-reliant semiconductor strategy.

WHY SEMICONDUCTOR CHIP DESIGN MATTERS?

Semiconductor design is the highest value part of the chip value chain.
It contributes:
- Up to 50% of total value addition,
- Around 20–50% of the Bill of Materials (BoM) cost,
- Nearly 30–35% of global semiconductor sales through the fabless model.
Even if chips are manufactured locally, without design capability, a country remains dependent on imported core technologies.
Strong fabless design capacity helps a country own intellectual property, reduce imports, and gain strategic control.

BACKGROUND: INDIA’S SEMICONDUCTOR PUSH

Semiconductor chips are critical for defence, space, telecom, healthcare, transport, AI, and digital infrastructure.
Global chip manufacturing is concentrated in a few regions, making supply chains fragile and geopolitically risky.
To address this, India launched the Semicon India Programme and the India Semiconductor Mission (ISM) to build an end-to-end ecosystem.
The DLI Scheme focuses specifically on chip design, where capital needs are lower but value creation is high.

WHAT IS DESIGN LINKED INCENTIVE SCHEME?

The DLI Scheme is implemented by the Ministry of Electronics and Information Technology under the Semicon India Programme.
Its aim is to create a self-reliant, globally competitive fabless semiconductor design ecosystem.
It supports Indian startups, MSMEs, and domestic companies in design, development, and deployment of semiconductor products.

WHO IS ELIGIBLE?

Startups: As per DPIIT notification (2019).
MSMEs: As per MSME Ministry notification (2020).
Domestic companies: Owned and controlled by resident Indian citizens as per FDI norms.
Startups and MSMEs receive financial incentives + design infrastructure support.
Other domestic companies receive financial incentives for deployment.

WHAT TYPES OF DESIGNS ARE SUPPORTED?

Integrated Circuits (ICs)
Chipsets
Systems-on-Chip (SoCs)
Systems and semiconductor IP cores
Semiconductor-linked designs across the full lifecycle, from idea to deployment.

FINANCIAL INCENTIVES UNDER DLI

Product Design Linked Incentive

Deployment Linked Incentive

Incentive of 4% to 6% of net sales turnover for five years.
Maximum cap of ₹30 crore per application.
Minimum cumulative sales requirement:
- ₹1 crore for startups and MSMEs,
- ₹5 crore for other domestic companies.
Design must be successfully deployed in electronic products.

DESIGN INFRASTRUCTURE SUPPORT (CHIP IN CENTRE)

Implemented by Centre for Development of Advanced Computing (C-DAC).
Key facilities provided:
- National EDA Tool Grid for remote access to advanced chip design software.
- IP Core Repository for SoC development.
- MPW prototyping support for chip fabrication at foundries.
- Post-silicon validation support for testing and silicon bring-up.

ACHIEVEMENTS SO FAR (AS OF JAN 2026)

CHIP IN & EDA GRADE IMPACT

ChipIN Centre supports nearly 1 lakh engineers and students across 400 organisations.
Covers 305 academic institutions under the Chips to Startup (C2S) Programme and 95 startups under DLI.
India’s shared EDA Grid recorded over 54 lakh hours of usage, showing strong adoption nationwide.
Entry barriers for early-stage innovators have reduced significantly.

KEY INSTITUTIONAL SUPPORT CENTRE

MeitY: Policy leadership and coordination of semiconductor initiatives.
Semicon India Programme: ₹76,000 crore outlay covering design, fabrication, and productization.
India Semiconductor Mission (ISM): End-to-end ecosystem development.
Chips to Startup (C2S) Programme: Training 85,000 industry-ready engineers.
Microprocessor Development Programme: Development of indigenous processors like VEGA, SHAKTI, and AJIT.

SUCCESS STORIES UNDER DLI

Vervesemi Microelectronics: Motor-control chips for appliances, drones, and EVs; multiple patents and global customers.
InCore Semiconductors: Indigenous RISC-V processor IPs and the “Dolomite” processor for edge-AI and smartphones.
Netrasemi: India’s first indigenous AI SoC in 12 nm for secure surveillance and drones.
Aheesa Digital Innovations: Indigenous GPON broadband SoC using VEGA processors.
AAGYAVISION: Radar-on-chip solutions for all-weather sensing and drone detection.

WHY THIS SCHEME IS STRATEGICALLY IMPORTANT?

CONCLUSION

The Design Linked Incentive Scheme anchors India in the most value-intensive part of the semiconductor chain—chip design.
It is already delivering visible outcomes in the form of silicon-proven designs, patents, trained talent, and private investment.
As projects move from validation to productisation and volume deployment, Indian firms are emerging as credible global chip designers.
The DLI Scheme is not just an incentive programme; it is a foundation for India’s long-term technological and strategic autonomy.

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